1. Field of the Invention
The invention in general relates to the electrostatic discharge (ESD) protection devices in integrated circuits, and more particularly to an ESD device fabricated in a BiCMOS integrated circuit process.
2. Statement of the Problem
It is well-known that integrated circuits are susceptible to damage from electrostatic discharges, commonly referred to as ESD, usually applied inadvevtently during handling. Thus almost all integrated circuits contain devices for protecting against excessive voltages as may be caused by ESD. It is well-known that a thick-oxide MOSFET operating as a parasitic lateral NPN bipolar transistor in second breakdown mode provides excellent ESD protection. See C. Duwury, R. N. Rountree, and L. S. White, "Summary of the Most Effective Electrostatic Discharge Protection Circuits For MOS Memories and Their Observed Failure Modes", EOS/ESD Symposium Proceedings, 1983, pp. 181-184; R. B. Wilcox and R. E. Douchette, "The Elimination of Electrostatic Discharge Failures From Silicon Gate Logic Technologies", EOS/ESD Symposium Proceedings, 1985, pp. 1-4; and R. A. McPhee, C. Duwury, R. N. Rountree, and H. Domingos, "Thick Oxide Device ESD Performance Under Process Variations", EOS/ESD Symposium Proceedings, 1986, pp. 173-181. Further, it is well-known to utilize a metallization layer in the MOSFET fabrication process to form the gate of a thick-oxide MOSFET and to utilize the field oxide to form the gate oxide. See U.S. Pat. No. 4,692,781 issued to Robert N. Rountree and Troy H. Herndon; U.S. Pat. No. 4,745,450 issued to Marc D. Hartranft and Keith A. Garret; and U.S. Pat. No. 4,952,994 issued to Chong M. Lin. All of the above patents recognize the efficiency of utilizing the steps of the fabrication process for creating the circuitry that is being protected to also create the devices for providing ESD protection, as for example the metallization and field oxide steps being used to create the thick-oxide ESD MOSFET. See also U.S. Pat. No. 5,021,853 issued to Kaizad R. Mistry which discloses utilizing the polysilicon gate of the protected devices to make the gate of the protective device. In addition, the Hartranft patent cited above discloses utilizing the same diffusion that is used to form resistors in the protective circuit to form the source/drains of the ESD MOSFET.
A problem in fabricating an ESD MOSFET is that the ESD device must be capable of handling much higher voltages and currents than the devices in the protected circuitry. A principle failure mode of ESD MOSFETs is electrothermomigration of materials at the drain contacts or even melting of the drain contacts due to the heat generated by the high currents. In order to avoid such problems, in fabricating the protective transistor, all of the references cited above, except perhaps the Rountree patent, use one or more additional process steps, beyond the steps already utilized in-fabricating the protected circuitry. For example, the Lin patent cited above discloses forming deep wells about the conventional source/drains to enable the protective transistor to handle larger currents, which deep wells are formed in a separate step from the conventional source/drains.
A principal thrust of integrated circuit technology is to make individual components of the integrated circuit smaller so as to obtain the advantages of less bulk, greater reliability, and faster response times. As integrated circuits become smaller, the distances between conductors and the thicknesses of insulating layers in transistors, capacitors and other electronic components in the individual IC devices become smaller, increasing the need for ESD protection. However, while the importance of the ESD protective devices being as compact as possible is recognized in all of the above references, all of the protective devices disclosed take up substantially more area than the corresponding devices in the protected circuitry. For example both the Rountree and Mistry patents cited above disclose making the distance between the transistor channel and drain contact three or more times larger in the ESD transistor than the protected transistor in order to prevent the drain contact melting problem mentioned above. Structures that can handle large voltages, in the range of 6000 volts, such as the device of the Rountree patent, cover several hundred square microns. Such a large size is not compatible with objective of ever-smaller integrated circuits. Further, these large ESD devices have turn-on times that are relatively slow. The faster the turn-on time of an ESD protective device, the less chance there is that an ESD voltage will build up to a significant level before the device turns on. As integrated circuits become ever more susceptible to damage from excess voltages, it becomes more important that the turn on time for the ESD devices be improved.
Thus, there is a need for an ESD transistor structure that is of the order of tens of square microns, has faster turn-on times, and the fabrication process for which requires no extra fabrication steps in addition to those already utilized in fabricating the protected circuit.
All of the references cited above disclose MOSFET ESD devices which are fabricated utilizing CMOS or MOS technology. Generally in bipolar technology the ESD devices of the prior art are diodes. In recent years the requirements of advanced technology have given rise to new fabrication processes such as BiCMOS, which combines both bipolar and CMOS devices on a single chip. A structure and process for fabricating ESD protective thick-oxide transistors that utilizes the BiCMOS technology and at the same time solves the problems outlined above would be highly desirable.
3. Solution to the problem
The present invention solves the above problems by providing a thick-oxide FET that is fabricated using only the process steps which are already used in state-of-the-art BiCMOS technology. The FETs occupy areas in the integrated circuit on the order of tens of square microns and have turn-on times significantly faster than prior art ESD devices that are capable of handling large voltages.
The invention impedes the drain contact melting by utilizing polysilicon as the source/drain contact. In one embodiment the invention utilizes the polysilicon of the base contact in the standard double-poly BiCMOS process to make the ESD transistor source/drain contacts. In another embodiment the invention utilizes the polysilicon of the emitter contact in the standard BiCMOS process to make the ESD transistor source/drain contacts.
The use of polysilicon for the source/drain contacts permits the creation of an outdiffusion into the source/drain which improves the ohmicity of the contact, thereby further enabling the ESD FET to handle large currents, which further reduces the heating problem.
The invention also addresses the problem of handling large currents without unduly increasing the area occupied by the ESD device by utilizing a standard BiCMOS process to create source drain regions that are much deeper than the ESD source/drains of the prior art. In one embodiment the resistor diffusion is used to make an enlarged well about the source/drain outdiffusion. In another embodiment the collector reach through doping of the BiCMOS process is used to make deep source/drain wells that can handle substantially increased current as compared to the prior art.
The invention further solves the high current problem by utilizing the deep wells characteristic of the portion of the BiCMOS process in which the CMOS transistors are fabricated to form a deep base for the parasitic bipolar transistor that, in combination with the deep sources and drains discussed above, increases the current handling capability of the parasitic transistor. In one embodiment the N-well of the P-channel CMOS transistor is use to form the base of a parasitic PNP bipolar transistor, and in another embodiment the P-well of the N-channel CMOS transistor is used to form the base of a parasitic NPN bipolar transistor.
The above features of the invention result in ESD devices that have areas of only about 10 to 100 square microns, have turn on times of on the order of 10 picoseconds, and yet are capable of handling charges as high as 6000 volts.